Complex integrated circuits (“ICs”) typically include a very large number of input and output (“I/O”) pins. For example, practical electronic devices may include hundreds and even thousands of I/O pins. Conventional testing of an IC having a high number of I/O pins is best accomplished with a test fixture having at least the same number of test channels (otherwise, only a portion of the IC I/O pins can be directly tested at any given time). A test fixture or board having hundreds or thousands of I/O channels, however, can be very expensive to manufacture. Furthermore, although a test fixture or board having a very large number of I/O channels may be suitable for use with a current generation of IC devices, it may quickly become obsolete (or inefficient) as newer, higher pin count devices are developed and manufactured. Accordingly, a need exists for an automated test system and technique for testing high pin count ICs with an “older generation” test fixture, where the number of I/O test channels in the test fixture is less than the number of I/O pins on the IC.